// **************************************************************
// Copyright (c) 2021 Xidian University.
// File name     : double_bus.v
// Module name   : 
// Created Date  : 2022-04
// Author        : Guowei/Xuyang
// Email         : 
// -------------------------------------------------------------------------
// Version       : 
// Last Modified : 2022-07-02 12:44:08
// Modified By   : Wangzekun
// -------------------------------------------------------------------------
// 
// -------------------------------------------------------------------------
// HISTORY       : v0.4
// Date         By  Comments
// ------------ --  ----------------------------------------------------------
// v0.1--Guowei/Xuyang
// v0.2--add scan_ME module and modify interface to suit 21 bit address
// v0.3--add DMA and corrspond interface AHB and AXI,modify module name to double_bus
// v0.4--delete output to input direct
module double_bus #(
    // parameter frame_mac_dst_bus0 = 48'h1000_0000_0001,
    // parameter frame_mac_src_bus0 = 48'h1000_0000_0002,
    parameter frame_length_bus0  = 16'h88b6          ,
    // parameter CLUSTER_ID0 = 2'b00,

    // parameter frame_mac_dst_bus1 = 48'h1000_0000_0001,
    // parameter frame_mac_src_bus1 = 48'h1000_0000_0002,
    parameter frame_length_bus1  = 16'h88b6,
    // parameter CLUSTER_ID1 = 2'b01,
    
    // parameter integer NP_DMA_BASE_ADDR     = 32'h8FFF_0000,
    parameter integer MAC_USER_WIDTH       = 4,  //Width of AXI-Stream USER channel
    parameter integer AXI_BURST_LEN        = 256,
    parameter integer AXI_ID_WIDTH         = 6,
    parameter integer AXI_ADDR_WIDTH       = 40,
    parameter integer AXI_DATA_WIDTH       = 128,
    parameter integer AXI_LIB_WIDTH        = 11, //Width of Max Transmit Length(in BYTES)
    parameter integer AXI_AWUSER_WIDTH     = 1,
    parameter integer AXI_ARUSER_WIDTH     = 1,
    parameter integer AXI_WUSER_WIDTH      = 1,
    parameter integer AXI_RUSER_WIDTH      = 1,
    parameter integer AXI_BUSER_WIDTH      = 1
    )(
//parameter
    input  wire [47:0]    frame_mac_dst_bus0,
    input  wire [47:0]    frame_mac_src_bus0,
    input  wire  [1:0]    cluster_id_bus0,
    input  wire [47:0]    frame_mac_dst_bus1,
    input  wire [47:0]    frame_mac_src_bus1,
    input  wire  [1:0]    cluster_id_bus1,
    input  wire [31:0]    dma_addr,
//vss&vdd
    inout  wire           vp           ,    
    inout  wire           vpdig        ,
    inout  wire           vph          ,   
    inout  wire           vptx0        ,
    inout  wire           vptx1        ,
    inout  wire           vptx2        ,
    inout  wire           vptx3        , 
    inout  wire           vsscore_0    ,
    inout  wire           vsscore_1    ,
    inout  wire           vsscore_2    ,
    inout  wire           gd           ,

    inout  wire           vp_1         ,    
    inout  wire           vpdig_1      ,
    inout  wire           vph_1        ,   
    inout  wire           vptx0_1      ,
    inout  wire           vptx1_1      ,
    inout  wire           vptx2_1      ,
    inout  wire           vptx3_1      , 
    inout  wire           vsscore_0_1  ,
    inout  wire           vsscore_1_1  ,
    inout  wire           vsscore_2_1  ,
    inout  wire           gd_1         ,
    
    //phy_mac_interface
    input  wire [16:0]    phy_ctrl_register  ,
    input  wire [25:0]    reset_register     ,
    input  wire [ 8:0]    req_lb_register    ,
    output wire [ 8:0]    ack_register_temp  ,//output在subsys�? np_reg_sync
    input  wire [11:0]    mac_pcs_status_register1,
    output wire [27:0]    mac_pcs_status_register0_temp,
    output wire [16:0]    mac_pcs_status_register2_temp,

    input  wire [16:0]    phy_ctrl_register_1               ,
    input  wire [25:0]    reset_register_1                  ,
    input  wire [ 8:0]    req_lb_register_1                 ,
    output wire [ 8:0]    ack_register_temp_1               ,//output在subsys�? np_reg_sync
    input  wire [11:0]    mac_pcs_status_register1_1        ,
    output wire [27:0]    mac_pcs_status_register0_temp_1   ,
    output wire [16:0]    mac_pcs_status_register2_temp_1   ,
    
    //jtag signals
    input  wire           jtag_tck              ,
    input  wire           jtag_tdi              ,
    output wire           jtag_tdo              ,
    output wire           jtag_tdo_en           ,
    input  wire           jtag_tms              ,
    input  wire           jtag_trst_n           ,

    input  wire           jtag_tck_1              ,
    input  wire           jtag_tdi_1              ,
    output wire           jtag_tdo_1              ,
    output wire           jtag_tdo_en_1           ,
    input  wire           jtag_tms_1              ,
    input  wire           jtag_trst_n_1           ,
     
    //clk and clk_en
    inout  wire           ref_pad_clk_m         ,
    inout  wire           ref_pad_clk_p         , 
    input  wire           ref_alt_clk_m         ,
    input  wire           ref_alt_clk_p         ,

    inout  wire           ref_pad_clk_m_1         ,
    inout  wire           ref_pad_clk_p_1         , 
    input  wire           ref_alt_clk_m_1         ,
    input  wire           ref_alt_clk_p_1         ,
        
    //Resistor Tune Signals
    inout   wire          resref                ,
    inout   wire          resref_1          ,

    //serial data signals
    input  wire           res_ack_in          ,
    output wire           res_ack_out         ,
    input  wire           res_req_in          ,
    output wire           res_req_out         ,

    input  wire           res_ack_in_1          ,
    output wire           res_ack_out_1         ,
    input  wire           res_req_in_1          ,
    output wire           res_req_out_1         ,
    
    inout  wire           rx0_m                 ,
    inout  wire           rx0_p                 ,
    inout  wire           rx1_m                 ,
    inout  wire           rx1_p                 ,
    inout  wire           rx2_m                 ,
    inout  wire           rx2_p                 ,
    inout  wire           rx3_m                 ,
    inout  wire           rx3_p                 ,

    inout  wire           rx0_m_1                 ,
    inout  wire           rx0_p_1                 ,
    inout  wire           rx1_m_1                 ,
    inout  wire           rx1_p_1                 ,
    inout  wire           rx2_m_1                 ,
    inout  wire           rx2_p_1                 ,
    inout  wire           rx3_m_1                 ,
    inout  wire           rx3_p_1                 ,
    
    inout  wire         tx0_m                ,
    inout  wire         tx0_p                ,
    inout  wire         tx1_m                ,
    inout  wire         tx1_p                ,
    inout  wire         tx2_m                ,
    inout  wire         tx2_p                ,
    inout  wire         tx3_m                ,
    inout  wire         tx3_p                ,

    inout  wire         tx0_m_1                ,
    inout  wire         tx0_p_1                ,
    inout  wire         tx1_m_1                ,
    inout  wire         tx1_p_1                ,
    inout  wire         tx2_m_1                ,
    inout  wire         tx2_p_1                ,
    inout  wire         tx3_m_1                ,
    inout  wire         tx3_p_1                ,
    
    //mac signals
    input  wire           ref_ff_clk_630plus    ,
    input  wire           reg_clk               ,

    input  wire           ref_ff_clk_630plus_1    ,
    input  wire           reg_clk_1               ,
    
    input  wire           xpcs_reg_wren       ,
    input  wire           xpcs_reg_rden       ,
    input  wire [15:0]    xpcs_reg_addr       ,
    input  wire [15:0]    xpcs_reg_din        ,
    output wire [15:0]    xpcs_reg_dout       ,
    output wire           xpcs_reg_busy       ,

    input  wire           xpcs_reg_wren_1       ,
    input  wire           xpcs_reg_rden_1       ,
    input  wire [15:0]    xpcs_reg_addr_1       ,
    input  wire [15:0]    xpcs_reg_din_1        ,
    output wire [15:0]    xpcs_reg_dout_1       ,
    output wire           xpcs_reg_busy_1       ,
    
    input  wire           xlpcs_reg_wren      ,
    input  wire           xlpcs_reg_rden      ,
    input  wire [15:0]    xlpcs_reg_addr      ,
    input  wire [15:0]    xlpcs_reg_din       ,
    output wire [15:0]    xlpcs_reg_dout      ,
    output wire           xlpcs_reg_busy      ,

    input  wire           xlpcs_reg_wren_1      ,
    input  wire           xlpcs_reg_rden_1      ,
    input  wire [15:0]    xlpcs_reg_addr_1      ,
    input  wire [15:0]    xlpcs_reg_din_1       ,
    output wire [15:0]    xlpcs_reg_dout_1      ,
    output wire           xlpcs_reg_busy_1      ,
    
    input  wire           mac_reg_wren         ,
    input  wire           mac_reg_rden         ,
    input  wire [ 7:0]    mac_reg_addr        ,
    input  wire [31:0]    mac_reg_din         ,
    output wire [31:0]    mac_reg_dout        ,
    output wire           mac_reg_busy        ,
    input  wire           mac_reg_lowp_ena    , 

    input  wire           mac_reg_wren_1         ,
    input  wire           mac_reg_rden_1         ,
    input  wire [ 7:0]    mac_reg_addr_1        ,
    input  wire [31:0]    mac_reg_din_1         ,
    output wire [31:0]    mac_reg_dout_1        ,
    output wire           mac_reg_busy_1        ,
    input  wire           mac_reg_lowp_ena_1    , 

    output wire [63:0]    mac_tx_ts           ,
    input  wire [63:0]    mac_frc_in_tx       ,
    input  wire [63:0]    mac_frc_in_rx       ,

    output wire [63:0]    mac_tx_ts_1           ,
    input  wire [63:0]    mac_frc_in_tx_1       ,
    input  wire [63:0]    mac_frc_in_rx_1       ,
  
  //---------------------------------------------------------------
  //fp_and_sch_top
  //---------------------------------------------------------------
    input         pkt_clk                 ,
    input         pkt_rstn                ,
    output        fp_sch_init_done        ,//with jtag

    input         pkt_clk_1               ,
    input         pkt_rstn_1              ,
    output        fp_sch_init_done_1      ,//with jtag
    //with CPU config，with jtag
    //ME1-ME6 ahb
    input  wire [31:0]np_data_in     ,//with interface,原mac 100 top
    input  wire [16:0]np_addr_in     ,
    input  wire       np_wr_in       ,
    input  wire       np_rd_in       ,
    output wire [31:0]np_data_out    ,//with jtag
    output wire       bus_np_data_out_vld,
    //input  wire [45:0]bus_np_addr_ctrl   ,

    input  wire [31:0]np_data_in_1     ,//with interface,原mac 100 top
    input  wire [16:0]np_addr_in_1     ,
    input  wire       np_wr_in_1       ,
    input  wire       np_rd_in_1       ,
    output wire [31:0]np_data_out_1    ,//with jtag
    output wire       bus_np_data_out_vld_1,
    //input  wire [45:0]bus_np_addr_ctrl_1   ,
  
    //  with other bus's fp
    //  bus1/2 is single bus output, bus3/4 is from other single bus
    output wire [9:0]   bus1_table_addr2            ,
    output wire [9:0]   bus1_table_ram_addr_convert ,
    output wire [71:0]  bus1_table_data2            ,
    output wire [71:0]  bus1_table_ram_data_convert ,
    output wire         bus1_table_wren2            ,
    output wire         bus1_table_ram_wr_en_convert,

    output wire [9:0]   bus2_table_addr2            ,
    output wire [9:0]   bus2_table_ram_addr_convert ,
    output wire [71:0]  bus2_table_data2            ,
    output wire [71:0]  bus2_table_ram_data_convert ,
    output wire         bus2_table_wren2            ,
    output wire         bus2_table_ram_wr_en_convert,

    input  wire [9:0]   bus3_table_addr2            ,
    input  wire [9:0]   bus3_table_ram_addr_convert ,
    input  wire [71:0]  bus3_table_data2            ,
    input  wire [71:0]  bus3_table_ram_data_convert ,
    input  wire         bus3_table_wren2            ,
    input  wire         bus3_table_ram_wr_en_convert,

    input  wire [9:0]   bus4_table_addr2            ,
    input  wire [9:0]   bus4_table_ram_addr_convert ,
    input  wire [71:0]  bus4_table_data2            ,
    input  wire [71:0]  bus4_table_ram_data_convert ,
    input  wire         bus4_table_wren2            ,
    input  wire         bus4_table_ram_wr_en_convert,

  //with crossbar
    input wire          uni_tx_rdy00                ,
    input wire          uni_tx_rdy01                ,
    input wire          uni_tx_rdy02                ,
    input wire          uni_tx_rdy03                ,
    input wire          mul_tx_rdy00                ,
    input wire          mul_tx_rdy01                ,
    input wire          mul_tx_rdy02                ,
    input wire          mul_tx_rdy03                ,

    input wire          uni_tx_rdy00_1                ,
    input wire          uni_tx_rdy01_1                ,
    input wire          uni_tx_rdy02_1                ,
    input wire          uni_tx_rdy03_1                ,
    input wire          mul_tx_rdy00_1                ,
    input wire          mul_tx_rdy01_1                ,
    input wire          mul_tx_rdy02_1                ,
    input wire          mul_tx_rdy03_1                ,
  
    output wire [255:0] emac_data_in              ,
    output wire         emac_data_wren            ,
    output wire [  5:0] rx_address_dpram          ,
    output wire [  3:0] mac_dest_port_in          ,
    output wire         mul_indicate              ,

    output wire [255:0] emac_data_in_1              ,
    output wire         emac_data_wren_1            ,
    output wire [  5:0] rx_address_dpram_1          ,
    output wire [  3:0] mac_dest_port_in_1          ,
    output wire         mul_indicate_1              ,

    input wire           pkt_sop_i  ,
    input wire [255:0]   pkt_data_i ,
    input wire           pkt_eop_i  ,
    input wire [4:0]     pkt_mod_i  ,
    input wire           pkt_dval_i ,

    input wire           pkt_sop_i_1  ,
    input wire [255:0]   pkt_data_i_1 ,
    input wire           pkt_eop_i_1  ,
    input wire [4:0]     pkt_mod_i_1  ,
    input wire           pkt_dval_i_1 ,
  //---------------------------------------------------------------
  //mac to np
  //---------------------------------------------------------------
    input [  9:0] ram_2p_cfg_register,
    input [ 11:0] ram_dp_cfg_register,
    input [  6:0] rf_2p_cfg_register,

  `ifdef SIM
    output wire         bus_axi_valid_o,
    output wire [255:0] bus_axi_data_o,
    output wire         bus_axi_last_o,
    output wire [ 31:0] bus_axi_keep_o,
    input  wire         bus_axi_ready_o,

    output wire         bus_axi_valid_o_1   ,
    output wire [255:0] bus_axi_data_o_1    ,
    output wire         bus_axi_last_o_1    ,
    output wire [ 31:0] bus_axi_keep_o_1    ,
    input  wire         bus_axi_ready_o_1   ,
    
    input  wire         bus_axi_valid_i,
    input  wire [255:0] bus_axi_data_i,
    input  wire         bus_axi_last_i,
    input  wire [ 31:0] bus_axi_keep_i,
    output wire         bus_axi_ready_i,

    input  wire         bus_axi_valid_i_1   ,
    input  wire [255:0] bus_axi_data_i_1    ,
    input  wire         bus_axi_last_i_1    ,
    input  wire [ 31:0] bus_axi_keep_i_1    ,
    output wire         bus_axi_ready_i_1   ,
  `endif 
  
  output       emac_rx_ready,//with crosssbar
  output       emac_rx_ready_1,

  // DMA interface signals
  // AHB Inputs
  input  wire                 HCLK,      // AHB clock
  input  wire                 HRESETn,   // system bus reset
  input  wire                 HSEL,      // AHB peripheral select
  input  wire                 HREADY,    // AHB ready input
  input  wire  [1:0]          HTRANS,    // AHB transfer type
  input  wire  [2:0]          HSIZE,     // AHB hsize
  input  wire                 HWRITE,    // AHB hwrite
  input  wire [31:0]          HADDR,     // AHB address bus
  input  wire [31:0]          HWDATA,    // AHB write data bus
  // AHB Outputs
  output wire                 HREADYOUT, // AHB ready output to S->M mux
  output wire                 HRESP,     // AHB response
  output wire [31:0]          HRDATA,

  // AXI_master interface
  input  wire                           m_axi_aclk_i,
  input  wire                           m_axi_aresetn_i,

  output wire [AXI_ID_WIDTH-1 : 0]      m_axi_awid_o,
  output wire [AXI_ADDR_WIDTH-1 : 0]    m_axi_awaddr_o,
  output wire [7 : 0]                   m_axi_awlen_o,
  output wire [2 : 0]                   m_axi_awsize_o,
  output wire [1 : 0]                   m_axi_awburst_o,
  output wire                           m_axi_awlock_o,
  output wire [3 : 0]                   m_axi_awcache_o,
  output wire [2 : 0]                   m_axi_awprot_o,
  output wire [3 : 0]                   m_axi_awqos_o,
  output wire [AXI_AWUSER_WIDTH-1 : 0]  m_axi_awuser_o,
  output wire                           m_axi_awvalid_o,
  input  wire                           m_axi_awready_i,

  output wire [AXI_DATA_WIDTH-1 : 0]    m_axi_wdata_o,
  output wire [AXI_DATA_WIDTH/8-1 : 0]  m_axi_wstrb_o,
  output wire                           m_axi_wlast_o,
  output wire [AXI_WUSER_WIDTH-1 : 0]   m_axi_wuser_o,
  output wire                           m_axi_wvalid_o,
  input  wire                           m_axi_wready_i,

  input  wire [AXI_ID_WIDTH-1 : 0]      m_axi_bid_i,
  input  wire [1 : 0]                   m_axi_bresp_i,
  input  wire [AXI_BUSER_WIDTH-1 : 0]   m_axi_buser_i,
  input  wire                           m_axi_bvalid_i,
  output wire                           m_axi_bready_o,

  output wire [AXI_ID_WIDTH-1 : 0]      m_axi_arid_o,
  output wire [AXI_ADDR_WIDTH-1 : 0]    m_axi_araddr_o,
  output wire [7 : 0]                   m_axi_arlen_o,
  output wire [2 : 0]                   m_axi_arsize_o,
  output wire [1 : 0]                   m_axi_arburst_o,
  output wire                           m_axi_arlock_o,
  output wire [3 : 0]                   m_axi_arcache_o,
  output wire [2 : 0]                   m_axi_arprot_o,
  output wire [3 : 0]                   m_axi_arqos_o,
  output wire [AXI_ARUSER_WIDTH-1 : 0]  m_axi_aruser_o,
  output wire                           m_axi_arvalid_o,
  input  wire                           m_axi_arready_i,
  
  input  wire [AXI_ID_WIDTH-1 : 0]      m_axi_rid_i,
  input  wire [AXI_DATA_WIDTH-1 : 0]    m_axi_rdata_i,
  input  wire [1 : 0]                   m_axi_rresp_i,
  input  wire                           m_axi_rlast_i,
  input  wire [AXI_RUSER_WIDTH-1 : 0]   m_axi_ruser_i,
  input  wire                           m_axi_rvalid_i,
  output wire                           m_axi_rready_o,

  output wire                           np_dma_irq_o, // NP DMA transmassion irq
//---------------------------------------------------------------
//dma channel sel , 2022.5.1 xym
//---------------------------------------------------------------
  input  wire [1 : 0]                  dma_channel_sel, // channel sel, 3 modes : 0x mode1, 10 mode2, 11 mode3

  // DFT port
  input  wire                          mbist_test,
  input  wire                          testmode ,
  input  wire                          se ,
  input  wire                          phy_scan_clk

);
wire  ff_clk;     //must be 156.25MHz to suit DMA
wire  ff_clk_1;   //must be 625MHz to suit DMA

//---------------------------------------------------------------
//cpt to dma/dma channel sel , 2022.5.1 xym
//---------------------------------------------------------------
wire         dma_rd_leng_en_0  ;
wire         dma_rd_data_en_0  ;
wire         dma_rd_leng_vld_0 ;
wire         dma_rd_dout_vld_0 ;
wire [ 10:0] dma_rd_leng_0     ;
wire [127:0] dma_rd_dout_0     ;
wire         dma_empty_0       ;
wire         dma_data_empty_0  ;//5.23 xym

wire         dma_axi_ttvalid_0 ;
wire         dma_axi_ttlast_0  ;
wire [  7:0] dma_axi_ttkeep_0  ;
wire [ 63:0] dma_axi_ttdata_0  ;
wire         dma_axi_ttready_0 ;

wire         dma_axi_rtvalid_0 ;
wire         dma_axi_rtlast_0  ;
wire [  7:0] dma_axi_rtkeep_0  ;
wire [ 63:0] dma_axi_rtdata_0  ;
wire         dma_axi_rtready_0 ;

wire         dma_rd_leng_en_1  ;
wire         dma_rd_data_en_1  ;
wire         dma_rd_leng_vld_1 ;
wire         dma_rd_dout_vld_1 ;
wire [ 10:0] dma_rd_leng_1     ;
wire [127:0] dma_rd_dout_1     ;
wire         dma_empty_1       ;
wire         dma_data_empty_1  ;//5.23 xym

wire         dma_axi_ttvalid_1 ;
wire         dma_axi_ttlast_1  ;
wire [  7:0] dma_axi_ttkeep_1  ;
wire [ 63:0] dma_axi_ttdata_1  ;
wire         dma_axi_ttready_1 ;

wire         dma_axi_rtvalid_1 ;
wire         dma_axi_rtlast_1  ;
wire [  7:0] dma_axi_rtkeep_1  ;
wire [ 63:0] dma_axi_rtdata_1  ;
wire         dma_axi_rtready_1 ;

// wire dma_reset_mux ;//liuyu,5.29
// assign dma_reset_mux = testmode ? ~m_axi_aresetn_i : reset_register[25] ;//liuyu,5.29

wire dma_reset_mux ; //high active
wire dma_reset_mux_1 ; //high active
hdfwd_rstp_sync i_dma_reset_mux ( dma_reset_mux, ff_clk, reset_register[25], ~pkt_rstn, testmode, 1'b0 );
hdfwd_rstp_sync i_dma_reset_mux_1 ( dma_reset_mux_1, ff_clk_1, reset_register[25], ~pkt_rstn, testmode, 1'b0 );

wire [  1:0] sel_dma_scope     ;

np_reg_sync #(.wid(2))
sel_sync_dma_scope(
  .d_clk(m_axi_aclk_i),
  .rst_n(m_axi_aresetn_i),
  .din(dma_channel_sel),
  .dout(sel_dma_scope)
);

single_bus #(
    // .frame_mac_dst_bus  (frame_mac_dst_bus0   ),
    // .frame_mac_src_bus  (frame_mac_src_bus0   ),
    .frame_length_bus   (frame_length_bus0    )
    // .CLUSTER_ID         (CLUSTER_ID0)
    )
    u_single_bus0(
//param
.frame_mac_dst(frame_mac_dst_bus0),
.frame_mac_src(frame_mac_src_bus0),
.cluster_id(cluster_id_bus0),
//-----------------------------------------------------------------------------------------
//phy信号
//-----------------------------------------------------------------------------------------
.vp          (vp)           ,
.vpdig       (vpdig)        ,
.vph         (vph)          ,
.vptx0       (vptx0)        ,
.vptx1       (vptx1)        ,
.vptx2       (vptx2)        ,
.vptx3       (vptx3)        ,
.vsscore_0   (vsscore_0)    ,
.vsscore_1   (vsscore_1)    ,
.vsscore_2   (vsscore_2)    ,
.gd          (gd)           ,

// phy_mac_interface
.phy_ctrl_register                   (phy_ctrl_register                 ),
.reset_register                      (reset_register                    ),
.req_lb_register                     (req_lb_register                   ),
.ack_register_temp                   (ack_register_temp                 ),
.mac_pcs_status_register1            (mac_pcs_status_register1          ),
.mac_pcs_status_register0_temp       (mac_pcs_status_register0_temp     ),
.mac_pcs_status_register2_temp       (mac_pcs_status_register2_temp     ),

//jtag signals
.jtag_tck               (jtag_tck        ),
.jtag_tdi               (jtag_tdi        ),
.jtag_tdo               (jtag_tdo        ),
.jtag_tdo_en            (jtag_tdo_en     ),
.jtag_tms               (jtag_tms        ),
.jtag_trst_n            (jtag_trst_n     ),

//clk and clk_en
.ref_pad_clk_m          (ref_pad_clk_m         ),
.ref_pad_clk_p          (ref_pad_clk_p         ),
.ref_alt_clk_m          (ref_alt_clk_m         ),//156
.ref_alt_clk_p          (ref_alt_clk_p         ),

//Resistor Tune Signals
.resref                 (resref               ),

//serial data signals
.res_ack_in     (res_ack_in ),
.res_ack_out    (res_ack_out),
.res_req_in     (res_req_in ),
.res_req_out    (res_req_out),

.rx0_m      (rx0_m),//in&out
.rx0_p      (rx0_p),
.rx1_m      (rx1_m),
.rx1_p      (rx1_p),
.rx2_m      (rx2_m),
.rx2_p      (rx2_p),
.rx3_m      (rx3_m),
.rx3_p      (rx3_p),
        
.tx0_m      (tx0_m),
.tx0_p      (tx0_p),
.tx1_m      (tx1_m),
.tx1_p      (tx1_p),
.tx2_m      (tx2_m),
.tx2_p      (tx2_p),
.tx3_m      (tx3_m),
.tx3_p      (tx3_p),

//mac signals
.ref_ff_clk_630plus       (ref_ff_clk_630plus   ),
.reg_clk                  (reg_clk              ),

.xpcs_reg_wren     (xpcs_reg_wren ),
.xpcs_reg_rden     (xpcs_reg_rden ),
.xpcs_reg_addr     (xpcs_reg_addr ),
.xpcs_reg_din      (xpcs_reg_din  ),
.xpcs_reg_dout     (xpcs_reg_dout ),
.xpcs_reg_busy     (xpcs_reg_busy ),

.xlpcs_reg_wren    (xlpcs_reg_wren),
.xlpcs_reg_rden    (xlpcs_reg_rden),
.xlpcs_reg_addr    (xlpcs_reg_addr),
.xlpcs_reg_din     (xlpcs_reg_din ),
.xlpcs_reg_dout    (xlpcs_reg_dout),
.xlpcs_reg_busy    (xlpcs_reg_busy),

.mac_reg_wren      (mac_reg_wren    ),
.mac_reg_rden      (mac_reg_rden    ),
.mac_reg_addr      (mac_reg_addr    ),
.mac_reg_din       (mac_reg_din     ),
.mac_reg_dout      (mac_reg_dout    ),
.mac_reg_busy      (mac_reg_busy    ),
.mac_reg_lowp_ena  (1'b0            ),

.mac_tx_ts         (mac_tx_ts       ),
.mac_frc_in_tx     (mac_frc_in_tx   ),
.mac_frc_in_rx     (mac_frc_in_rx   ),

//---------------------------------------------------------------
//fp_and_sch_top
//---------------------------------------------------------------
.pkt_clk                (pkt_clk                  ),
.pkt_rstn               (pkt_rstn                 ),
.fp_sch_init_done       (fp_sch_init_done         ),
.hclk_i			(HCLK			  ),
.hresetn_i		(HRESETn		  ),
//进入bus后有逻辑交叉
.np_data_in             (np_data_in                ),
.np_addr_in             (np_addr_in                ),
.np_wr_in               (np_wr_in                  ),
.np_rd_in               (np_rd_in                  ),
.np_data_out            (np_data_out               ),
.bus_np_data_out_vld    (bus_np_data_out_vld       ),
// .bus_np_addr_ctrl       //(bus_np_addr_ctrl          ),

// bus1 is single bus output, bus2/3/4 is from other single bus
.bus1_table_addr2               (bus1_table_addr2            ),
.bus1_table_ram_addr_convert    (bus1_table_ram_addr_convert ),
.bus1_table_data2               (bus1_table_data2            ),
.bus1_table_ram_data_convert    (bus1_table_ram_data_convert ),
.bus1_table_wren2               (bus1_table_wren2            ),
.bus1_table_ram_wr_en_convert   (bus1_table_ram_wr_en_convert),

.bus2_table_addr2               (bus2_table_addr2            ),
.bus2_table_ram_addr_convert    (bus2_table_ram_addr_convert ),
.bus2_table_data2               (bus2_table_data2            ),
.bus2_table_ram_data_convert    (bus2_table_ram_data_convert ),
.bus2_table_wren2               (bus2_table_wren2            ),
.bus2_table_ram_wr_en_convert   (bus2_table_ram_wr_en_convert),

.bus3_table_addr2               (bus3_table_addr2            ),
.bus3_table_ram_addr_convert    (bus3_table_ram_addr_convert ),
.bus3_table_data2               (bus3_table_data2            ),
.bus3_table_ram_data_convert    (bus3_table_ram_data_convert ),
.bus3_table_wren2               (bus3_table_wren2            ),
.bus3_table_ram_wr_en_convert   (bus3_table_ram_wr_en_convert),

.bus4_table_addr2               (bus4_table_addr2            ),
.bus4_table_ram_addr_convert    (bus4_table_ram_addr_convert ),
.bus4_table_data2               (bus4_table_data2            ),
.bus4_table_ram_data_convert    (bus4_table_ram_data_convert ),
.bus4_table_wren2               (bus4_table_wren2            ),
.bus4_table_ram_wr_en_convert   (bus4_table_ram_wr_en_convert),

.uni_tx_rdy00           (uni_tx_rdy00       ),
.uni_tx_rdy01           (uni_tx_rdy01       ),
.uni_tx_rdy02           (uni_tx_rdy02       ),
.uni_tx_rdy03           (uni_tx_rdy03       ),
.mul_tx_rdy00           (mul_tx_rdy00       ),
.mul_tx_rdy01           (mul_tx_rdy01       ),
.mul_tx_rdy02           (mul_tx_rdy02       ),
.mul_tx_rdy03           (mul_tx_rdy03       ),

.emac_data_in           (emac_data_in       ),   
.emac_data_wren         (emac_data_wren     ), 
.rx_address_dpram       (rx_address_dpram   ),
.mac_dest_port_in       (mac_dest_port_in   ),
.mul_indicate           (mul_indicate       ), 

.pkt_sop_i              (pkt_sop_i          ),
.pkt_data_i             (pkt_data_i         ),
.pkt_eop_i              (pkt_eop_i          ),
.pkt_mod_i              (pkt_mod_i          ),
.pkt_dval_i             (pkt_dval_i         ),
    
//---------------------------------------------------------------
//mac to np
//---------------------------------------------------------------
.ram_2p_cfg_register    (ram_2p_cfg_register),
.ram_dp_cfg_register    (ram_dp_cfg_register),
.rf_2p_cfg_register     (rf_2p_cfg_register) ,
`ifdef SIM
    bus_axi_valid_o         (bus_axi_valid_o   ),
    bus_axi_data_o          (bus_axi_data_o    ),
    bus_axi_last_o          (bus_axi_last_o    ),
    bus_axi_keep_o          (bus_axi_keep_o    ),
    bus_axi_ready_o         (bus_axi_ready_o   ),

    bus_axi_valid_i         (bus_axi_valid_i   ),
    bus_axi_data_i          (bus_axi_data_i    ),
    bus_axi_last_i          (bus_axi_last_i    ),
    bus_axi_keep_i          (bus_axi_keep_i    ),
    bus_axi_ready_i         (bus_axi_ready_i   ),
`endif

.emac_rx_ready          (emac_rx_ready     ),
.ff_clk                 (ff_clk),

//---------------------------------------------------------------
//cpt to dma , 2022.5.1 xym
//---------------------------------------------------------------
.dma_channel_sel   ( dma_channel_sel   ),
.sel_dma_scope     ( sel_dma_scope     ),
.dma_clk           ( m_axi_aclk_i      ),
.dma_rstn          ( m_axi_aresetn_i   ),
.dma_rd_leng_en_i  ( dma_rd_leng_en_0  ),
.dma_rd_data_en_i  ( dma_rd_data_en_0  ),
.dma_rd_leng_vld_o ( dma_rd_leng_vld_0 ),
.dma_rd_dout_vld_o ( dma_rd_dout_vld_0 ),
.dma_rd_leng_o     ( dma_rd_leng_0     ),
.dma_rd_dout_o     ( dma_rd_dout_0     ),
.dma_empty_o       ( dma_empty_0       ),
.dma_data_empty_o  ( dma_data_empty_0  ),//5.23 xym

.dma_axi_ttvalid   ( dma_axi_ttvalid_0 ),
.dma_axi_ttlast    ( dma_axi_ttlast_0  ),
.dma_axi_ttkeep    ( dma_axi_ttkeep_0  ),
.dma_axi_ttdata    ( dma_axi_ttdata_0  ),
.dma_axi_ttready   ( dma_axi_ttready_0 ),

.dma_axi_rtvalid   ( dma_axi_rtvalid_0 ),
.dma_axi_rtlast    ( dma_axi_rtlast_0  ),
.dma_axi_rtkeep    ( dma_axi_rtkeep_0  ),
.dma_axi_rtdata    ( dma_axi_rtdata_0  ),
.dma_axi_rtready   ( dma_axi_rtready_0 ),

// DFT port
.testmode          ( testmode          ),
.se                ( se                ),
.phy_scan_clk      ( phy_scan_clk      )
);

// #########################################################################################
//bus1
// #########################################################################################
single_bus #(
    // .frame_mac_dst_bus  (frame_mac_dst_bus1   ),
    // .frame_mac_src_bus  (frame_mac_src_bus1   ),
    .frame_length_bus   (frame_length_bus1    )
    // .CLUSTER_ID         (CLUSTER_ID1)
    )
    u_single_bus1(
//param
.frame_mac_dst(frame_mac_dst_bus1),
.frame_mac_src(frame_mac_src_bus1),
.cluster_id(cluster_id_bus1),
//-----------------------------------------------------------------------------------------
//phy信号
//-----------------------------------------------------------------------------------------
.vp          (vp_1          ),
.vpdig       (vpdig_1       ),
.vph         (vph_1         ),
.vptx0       (vptx0_1       ),
.vptx1       (vptx1_1       ),
.vptx2       (vptx2_1       ),
.vptx3       (vptx3_1       ),
.vsscore_0   (vsscore_0_1   ),
.vsscore_1   (vsscore_1_1   ),
.vsscore_2   (vsscore_2_1   ),
.gd          (gd_1          ),

// phy_mac_interface
.phy_ctrl_register                   (phy_ctrl_register_1                 ),
.reset_register                      (reset_register_1                    ),
.req_lb_register                     (req_lb_register_1                   ),
.ack_register_temp                   (ack_register_temp_1                 ),
.mac_pcs_status_register1            (mac_pcs_status_register1_1          ),
.mac_pcs_status_register0_temp       (mac_pcs_status_register0_temp_1     ),
.mac_pcs_status_register2_temp       (mac_pcs_status_register2_temp_1     ),

//jtag signals
.jtag_tck               (jtag_tck_1        ),
.jtag_tdi               (jtag_tdi_1        ),
.jtag_tdo               (jtag_tdo_1        ),
.jtag_tdo_en            (jtag_tdo_en_1     ),
.jtag_tms               (jtag_tms_1        ),
.jtag_trst_n            (jtag_trst_n_1     ),

//clk and clk_en
.ref_pad_clk_m          (ref_pad_clk_m_1        ),
.ref_pad_clk_p          (ref_pad_clk_p_1        ),
.ref_alt_clk_m          (ref_alt_clk_m_1        ),//156
.ref_alt_clk_p          (ref_alt_clk_p_1        ),

//Resistor Tune Signals
.resref                 (resref_1               ),

//serial data signals
.res_ack_in     (res_ack_in_1 ),
.res_ack_out    (res_ack_out_1),
.res_req_in     (res_req_in_1 ),
.res_req_out    (res_req_out_1),

.rx0_m      (rx0_m_1),//in&out
.rx0_p      (rx0_p_1),
.rx1_m      (rx1_m_1),
.rx1_p      (rx1_p_1),
.rx2_m      (rx2_m_1),
.rx2_p      (rx2_p_1),
.rx3_m      (rx3_m_1),
.rx3_p      (rx3_p_1),
        
.tx0_m      (tx0_m_1),
.tx0_p      (tx0_p_1),
.tx1_m      (tx1_m_1),
.tx1_p      (tx1_p_1),
.tx2_m      (tx2_m_1),
.tx2_p      (tx2_p_1),
.tx3_m      (tx3_m_1),
.tx3_p      (tx3_p_1),

//mac signals
.ref_ff_clk_630plus       (ref_ff_clk_630plus_1     ),
.reg_clk                  (reg_clk_1                ),

.xpcs_reg_wren     (xpcs_reg_wren_1     ),
.xpcs_reg_rden     (xpcs_reg_rden_1     ),
.xpcs_reg_addr     (xpcs_reg_addr_1     ),
.xpcs_reg_din      (xpcs_reg_din_1      ),
.xpcs_reg_dout     (xpcs_reg_dout_1     ),
.xpcs_reg_busy     (xpcs_reg_busy_1     ),

.xlpcs_reg_wren    (xlpcs_reg_wren_1    ),
.xlpcs_reg_rden    (xlpcs_reg_rden_1    ),
.xlpcs_reg_addr    (xlpcs_reg_addr_1    ),
.xlpcs_reg_din     (xlpcs_reg_din_1     ),
.xlpcs_reg_dout    (xlpcs_reg_dout_1    ),
.xlpcs_reg_busy    (xlpcs_reg_busy_1    ),

.mac_reg_wren      (mac_reg_wren_1       ),
.mac_reg_rden      (mac_reg_rden_1       ),
.mac_reg_addr      (mac_reg_addr_1       ),
.mac_reg_din       (mac_reg_din_1        ),
.mac_reg_dout      (mac_reg_dout_1       ),
.mac_reg_busy      (mac_reg_busy_1       ),
.mac_reg_lowp_ena  (mac_reg_lowp_ena_1   ),
.mac_tx_ts         (mac_tx_ts_1          ),
.mac_frc_in_tx     (mac_frc_in_tx_1      ),
.mac_frc_in_rx     (mac_frc_in_rx_1      ),

//---------------------------------------------------------------
//fp_and_sch_top
//---------------------------------------------------------------
.pkt_clk                (pkt_clk_1                 ),
.pkt_rstn               (pkt_rstn_1                ),
.fp_sch_init_done       (fp_sch_init_done_1        ),
.hclk_i			(HCLK			   ),
.hresetn_i              (HRESETn                   ),
//进入bus后有逻辑交叉
.np_data_in             (np_data_in_1               ),
.np_addr_in             (np_addr_in_1               ),
.np_wr_in               (np_wr_in_1                 ),
.np_rd_in               (np_rd_in_1                 ),
.np_data_out            (np_data_out_1              ),
.bus_np_data_out_vld    (bus_np_data_out_vld_1      ),
// .bus_np_addr_ctrl       (bus_np_addr_ctrl_1         ),

// bus1 is single bus output, bus2/3/4 is from other single bus
.bus1_table_addr2               (bus2_table_addr2             ),
.bus1_table_ram_addr_convert    (bus2_table_ram_addr_convert  ),
.bus1_table_data2               (bus2_table_data2             ),
.bus1_table_ram_data_convert    (bus2_table_ram_data_convert  ),
.bus1_table_wren2               (bus2_table_wren2             ),
.bus1_table_ram_wr_en_convert   (bus2_table_ram_wr_en_convert ),

.bus2_table_addr2               (bus1_table_addr2             ),
.bus2_table_ram_addr_convert    (bus1_table_ram_addr_convert  ),
.bus2_table_data2               (bus1_table_data2             ),
.bus2_table_ram_data_convert    (bus1_table_ram_data_convert  ),
.bus2_table_wren2               (bus1_table_wren2             ),
.bus2_table_ram_wr_en_convert   (bus1_table_ram_wr_en_convert ),

.bus3_table_addr2               (bus3_table_addr2             ),
.bus3_table_ram_addr_convert    (bus3_table_ram_addr_convert  ),
.bus3_table_data2               (bus3_table_data2             ),
.bus3_table_ram_data_convert    (bus3_table_ram_data_convert  ),
.bus3_table_wren2               (bus3_table_wren2             ),
.bus3_table_ram_wr_en_convert   (bus3_table_ram_wr_en_convert ),

.bus4_table_addr2               (bus4_table_addr2             ),
.bus4_table_ram_addr_convert    (bus4_table_ram_addr_convert  ),
.bus4_table_data2               (bus4_table_data2             ),
.bus4_table_ram_data_convert    (bus4_table_ram_data_convert  ),
.bus4_table_wren2               (bus4_table_wren2             ),
.bus4_table_ram_wr_en_convert   (bus4_table_ram_wr_en_convert ),

.uni_tx_rdy00           (uni_tx_rdy00_1       ),
.uni_tx_rdy01           (uni_tx_rdy01_1       ),
.uni_tx_rdy02           (uni_tx_rdy02_1       ),
.uni_tx_rdy03           (uni_tx_rdy03_1       ),
.mul_tx_rdy00           (mul_tx_rdy00_1       ),
.mul_tx_rdy01           (mul_tx_rdy01_1       ),
.mul_tx_rdy02           (mul_tx_rdy02_1       ),
.mul_tx_rdy03           (mul_tx_rdy03_1       ),

.emac_data_in           (emac_data_in_1       ),   
.emac_data_wren         (emac_data_wren_1     ), 
.rx_address_dpram       (rx_address_dpram_1   ),
.mac_dest_port_in       (mac_dest_port_in_1   ),
.mul_indicate           (mul_indicate_1       ), 

.pkt_sop_i              (pkt_sop_i_1            ),
.pkt_data_i             (pkt_data_i_1           ),
.pkt_eop_i              (pkt_eop_i_1            ),
.pkt_mod_i              (pkt_mod_i_1            ),
.pkt_dval_i             (pkt_dval_i_1           ),
    
//---------------------------------------------------------------
//mac to np
//---------------------------------------------------------------
.ram_2p_cfg_register    (ram_2p_cfg_register),
.ram_dp_cfg_register    (ram_dp_cfg_register),
.rf_2p_cfg_register     (rf_2p_cfg_register) ,
`ifdef SIM
    bus_axi_valid_o         (bus_axi_valid_o_1   ),
    bus_axi_data_o          (bus_axi_data_o_1    ),
    bus_axi_last_o          (bus_axi_last_o_1    ),
    bus_axi_keep_o          (bus_axi_keep_o_1    ),
    bus_axi_ready_o         (bus_axi_ready_o_1   ),

    bus_axi_valid_i         (bus_axi_valid_i_1   ),
    bus_axi_data_i          (bus_axi_data_i_1    ),
    bus_axi_last_i          (bus_axi_last_i_1    ),
    bus_axi_keep_i          (bus_axi_keep_i_1    ),
    bus_axi_ready_i         (bus_axi_ready_i_1   ),
`endif

.emac_rx_ready          (emac_rx_ready_1     ),
.ff_clk                 (ff_clk_1),

//---------------------------------------------------------------
//cpt to dma , 2022.5.1 xym
//---------------------------------------------------------------
.dma_channel_sel   ( dma_channel_sel   ),
.sel_dma_scope     ( sel_dma_scope     ),
.dma_clk           ( m_axi_aclk_i      ),
.dma_rstn          ( m_axi_aresetn_i   ),
.dma_rd_leng_en_i  ( dma_rd_leng_en_1  ),
.dma_rd_data_en_i  ( dma_rd_data_en_1  ),
.dma_rd_leng_vld_o ( dma_rd_leng_vld_1 ),
.dma_rd_dout_vld_o ( dma_rd_dout_vld_1 ),
.dma_rd_leng_o     ( dma_rd_leng_1     ),
.dma_rd_dout_o     ( dma_rd_dout_1     ),
.dma_empty_o       ( dma_empty_1       ),
.dma_data_empty_o  ( dma_data_empty_1  ),//5.23 xym

.dma_axi_ttvalid   ( dma_axi_ttvalid_1 ),
.dma_axi_ttlast    ( dma_axi_ttlast_1  ),
.dma_axi_ttkeep    ( dma_axi_ttkeep_1  ),
.dma_axi_ttdata    ( dma_axi_ttdata_1  ),
.dma_axi_ttready   ( dma_axi_ttready_1 ),

.dma_axi_rtvalid   ( dma_axi_rtvalid_1 ),
.dma_axi_rtlast    ( dma_axi_rtlast_1  ),
.dma_axi_rtkeep    ( dma_axi_rtkeep_1  ),
.dma_axi_rtdata    ( dma_axi_rtdata_1  ),
.dma_axi_rtready   ( dma_axi_rtready_1 ),

// DFT port
.testmode          ( testmode          ),
.se                ( se                ),
.phy_scan_clk      ( phy_scan_clk      )
);

  //DMA
  np_dma_top #( 
     // .NP_DMA_BASE_ADDR       (NP_DMA_BASE_ADDR),
     .MAC_USER_WIDTH         (MAC_USER_WIDTH),
     .AXI_BURST_LEN          (AXI_BURST_LEN),
     .AXI_ID_WIDTH           (AXI_ID_WIDTH),
     .AXI_ADDR_WIDTH         (AXI_ADDR_WIDTH),
     .AXI_DATA_WIDTH         (AXI_DATA_WIDTH),
     .AXI_LIB_WIDTH          (AXI_LIB_WIDTH),
     .AXI_AWUSER_WIDTH       (AXI_AWUSER_WIDTH),
     .AXI_ARUSER_WIDTH       (AXI_ARUSER_WIDTH),
     .AXI_WUSER_WIDTH        (AXI_WUSER_WIDTH),
     .AXI_RUSER_WIDTH        (AXI_RUSER_WIDTH),
     .AXI_BUSER_WIDTH        (AXI_BUSER_WIDTH)
   )
    u_np_dma_top_0(
     // Parameter
    .dma_addr  (dma_addr ),
     // AHB input
    .HCLK      (HCLK     ),
    .HRESETn   (HRESETn  ),
    .HSEL      (HSEL     ),
    .HREADY    (HREADY   ),
    .HTRANS    (HTRANS   ),
    .HSIZE     (HSIZE    ),
    .HWRITE    (HWRITE   ),
    .HADDR     (HADDR    ),
    .HWDATA    (HWDATA   ),
     // AHB output
    .HREADYOUT (HREADYOUT),
    .HRESP     (HRESP    ),
    .HRDATA    (HRDATA   ),
`ifdef HDFWD_MAC_PHY_BYPASS
     // AXI stream 10G interface
    .axi_s0_clk_i            (),//ff_clk),//156.25MHz
    .axi_s0_resetn_i         (),//~dma_reset_mux),//liuyu529
     // AXI stream receive
    .bus0_axi_strm_rtvalid_i (),//dma_axi_rtvalid_0),
    .bus0_axi_strm_rtlast_i  (),//dma_axi_rtlast_0),
    .bus0_axi_strm_rtkeep_i  (),//dma_axi_rtkeep_0),
    .bus0_axi_strm_rtdata_i  (),//dma_axi_rtdata_0),
    .bus0_axi_strm_rtready_o (),//dma_axi_rtready_0),
     // AXI stream transmit
    .bus0_axi_strm_ttvalid_o (),//dma_axi_ttvalid_0),
    .bus0_axi_strm_ttlast_o  (),//dma_axi_ttlast_0),
    .bus0_axi_strm_ttkeep_o  (),//dma_axi_ttkeep_0),
    .bus0_axi_strm_ttdata_o  (),//dma_axi_ttdata_0),
    .bus0_axi_strm_ttready_i (),//dma_axi_ttready_0),

     // AXI stream 40G interface
    .axi_s1_clk_i            (),//ff_clk_1),//625MHz
    .axi_s1_resetn_i         (),//~dma_reset_mux),//liuyu529
     // AXI stream receive
    .bus1_axi_strm_rtvalid_i (),//dma_axi_rtvalid_1),
    .bus1_axi_strm_rtlast_i  (),//dma_axi_rtlast_1),
    .bus1_axi_strm_rtkeep_i  (),//dma_axi_rtkeep_1),
    .bus1_axi_strm_rtdata_i  (),//dma_axi_rtdata_1),
    .bus1_axi_strm_rtready_o (),//dma_axi_rtready_1),
     // AXI stream transmit
    .bus1_axi_strm_ttvalid_o (),//dma_axi_ttvalid_1),
    .bus1_axi_strm_ttlast_o  (),//dma_axi_ttlast_1),
    .bus1_axi_strm_ttkeep_o  (),//dma_axi_ttkeep_1),
    .bus1_axi_strm_ttdata_o  (),//dma_axi_ttdata_1),
    .bus1_axi_strm_ttready_i (),//dma_axi_ttready_1),
`else 
     // AXI stream 10G interface
    .axi_s0_clk_i            (ff_clk),//156.25MHz
    .axi_s0_resetn_i         (~dma_reset_mux),//liuyu529
     // AXI stream receive
    .bus0_axi_strm_rtvalid_i (dma_axi_rtvalid_0),
    .bus0_axi_strm_rtlast_i  (dma_axi_rtlast_0),
    .bus0_axi_strm_rtkeep_i  (dma_axi_rtkeep_0),
    .bus0_axi_strm_rtdata_i  (dma_axi_rtdata_0),
    .bus0_axi_strm_rtready_o (dma_axi_rtready_0),
     // AXI stream transmit
    .bus0_axi_strm_ttvalid_o (dma_axi_ttvalid_0),
    .bus0_axi_strm_ttlast_o  (dma_axi_ttlast_0),
    .bus0_axi_strm_ttkeep_o  (dma_axi_ttkeep_0),
    .bus0_axi_strm_ttdata_o  (dma_axi_ttdata_0),
    .bus0_axi_strm_ttready_i (dma_axi_ttready_0),

     // AXI stream 40G interface
    .axi_s1_clk_i            (ff_clk_1),//625MHz
    .axi_s1_resetn_i         (~dma_reset_mux_1),//liuyu529
     // AXI stream receive
    .bus1_axi_strm_rtvalid_i (dma_axi_rtvalid_1),
    .bus1_axi_strm_rtlast_i  (dma_axi_rtlast_1),
    .bus1_axi_strm_rtkeep_i  (dma_axi_rtkeep_1),
    .bus1_axi_strm_rtdata_i  (dma_axi_rtdata_1),
    .bus1_axi_strm_rtready_o (dma_axi_rtready_1),
     // AXI stream transmit
    .bus1_axi_strm_ttvalid_o (dma_axi_ttvalid_1),
    .bus1_axi_strm_ttlast_o  (dma_axi_ttlast_1),
    .bus1_axi_strm_ttkeep_o  (dma_axi_ttkeep_1),
    .bus1_axi_strm_ttdata_o  (dma_axi_ttdata_1),
    .bus1_axi_strm_ttready_i (dma_axi_ttready_1),
`endif
    .np_dma_irq_o            (np_dma_irq_o),
    // AXI master
    .m_axi_aclk_i            (m_axi_aclk_i),
    .m_axi_aresetn_i         (m_axi_aresetn_i),
    .m_axi_awid_o            (m_axi_awid_o),
    .m_axi_awaddr_o          (m_axi_awaddr_o),
    .m_axi_awlen_o           (m_axi_awlen_o),
    .m_axi_awsize_o          (m_axi_awsize_o),
    .m_axi_awburst_o         (m_axi_awburst_o),
    .m_axi_awlock_o          (m_axi_awlock_o),
    .m_axi_awcache_o         (m_axi_awcache_o),
    .m_axi_awprot_o          (m_axi_awprot_o),
    .m_axi_awqos_o           (m_axi_awqos_o),
    .m_axi_awuser_o          (m_axi_awuser_o),
    .m_axi_awvalid_o         (m_axi_awvalid_o),
    .m_axi_awready_i         (m_axi_awready_i),
    .m_axi_wdata_o           (m_axi_wdata_o),
    .m_axi_wstrb_o           (m_axi_wstrb_o),
    .m_axi_wlast_o           (m_axi_wlast_o),
    .m_axi_wuser_o           (m_axi_wuser_o),
    .m_axi_wvalid_o          (m_axi_wvalid_o),
    .m_axi_wready_i          (m_axi_wready_i),
    .m_axi_bid_i             (m_axi_bid_i),
    .m_axi_bresp_i           (m_axi_bresp_i),
    .m_axi_buser_i           (m_axi_buser_i),
    .m_axi_bvalid_i          (m_axi_bvalid_i),
    .m_axi_bready_o          (m_axi_bready_o),
    .m_axi_arid_o            (m_axi_arid_o),
    .m_axi_araddr_o          (m_axi_araddr_o),
    .m_axi_arlen_o           (m_axi_arlen_o),
    .m_axi_arsize_o          (m_axi_arsize_o),
    .m_axi_arburst_o         (m_axi_arburst_o),
    .m_axi_arlock_o          (m_axi_arlock_o),
    .m_axi_arcache_o         (m_axi_arcache_o),
    .m_axi_arprot_o          (m_axi_arprot_o),
    .m_axi_arqos_o           (m_axi_arqos_o),
    .m_axi_aruser_o          (m_axi_aruser_o),
    .m_axi_arvalid_o         (m_axi_arvalid_o),
    .m_axi_arready_i         (m_axi_arready_i),
    .m_axi_rid_i             (m_axi_rid_i),
    .m_axi_rdata_i           (m_axi_rdata_i),
    .m_axi_rresp_i           (m_axi_rresp_i),
    .m_axi_rlast_i           (m_axi_rlast_i),
    .m_axi_ruser_i           (m_axi_ruser_i),
    .m_axi_rvalid_i          (m_axi_rvalid_i),
    .m_axi_rready_o          (m_axi_rready_o),

    .dma_channel_sel_i       (sel_dma_scope),
    .dma_rd_leng_en_0_o      (dma_rd_leng_en_0), //from cpt
    .dma_rd_data_en_0_o      (dma_rd_data_en_0),
    .dma_rd_leng_vld_0_i     (dma_rd_leng_vld_0),
    .dma_rd_dout_vld_0_i     (dma_rd_dout_vld_0),
    .dma_rd_leng_0_i         (dma_rd_leng_0),
    .dma_rd_dout_0_i         (dma_rd_dout_0),
    .dma_empty_0_i           (dma_empty_0),
    .dma_data_empty_0_i      (dma_data_empty_0), //5.23 xym
    .dma_rd_leng_en_1_o      (dma_rd_leng_en_1),
    .dma_rd_data_en_1_o      (dma_rd_data_en_1),
    .dma_rd_leng_vld_1_i     (dma_rd_leng_vld_1),
    .dma_rd_dout_vld_1_i     (dma_rd_dout_vld_1),
    .dma_rd_leng_1_i         (dma_rd_leng_1),
    .dma_rd_dout_1_i         (dma_rd_dout_1),
    .dma_empty_1_i           (dma_empty_1),
    .dma_data_empty_1_i      (dma_data_empty_1), //5.23 xym
    .ram_dp_cfg_register     (ram_dp_cfg_register),
    .ram_2p_cfg_register     (ram_2p_cfg_register),
    .rf_2p_cfg_register      (rf_2p_cfg_register),
    
    // DFT port
    .mbist_test              (mbist_test),
    .testmode                (testmode)
  );

endmodule
